Memory systems can employ memory devices to store and access information. The memory devices can include volatile memory devices, non-volatile memory devices, or a combination device. Memory devices, such as dynamic random-access memory (DRAM), can utilize electrical energy to store and access data. Some memory devices can include vertically stacked dies (e.g., die stacks) that are connected using Through-Silicon-Vias (TSVs) in a master-slave (MS) configuration. For example, the memory devices can include Double Data Rate (DDR) RAM devices that implement DDR interfacing scheme for high-speed data transfer. The DDR RAM devices (e.g., DDR4 devices, DDR5 devices, etc.) can include memory chips that include die stacks that each include a master device and one or more slave device.
As illustrated in FIG. 1, a memory device 102 (e.g., DDR DRAM device) can be electrically coupled to a controller 103 (e.g., a memory controller, a central processing unit (CPU), etc.). The memory device 102 can respond to commands from the controller 103 and perform memory-related operations, such as reads or writes.
As discussed above, the memory device 102 can be a stacked device. As such, the memory device 102 can include a master device 104 and a set of slave devices 106. For example, the memory device 102 can be a 2H, a 4H, an 8H, or a 16H (e.g., two/four/eight/sixteen total dies with three/seven/fifteen slave dies) device. For the stacked device, the controller 103 can write to or read from the slave devices 106, but to do so, the controller 103 can communicate to/through the master device 104. For example, the master device 104 can include input/output (I/O) pads 112 and/or I/O buffers 114 used to communicate with an external device (e.g., the controller 103). The master device 104 can also include an operational logic 116 (e.g., control/read/write logic) configured to facilitate/communicate the commands/operations. The memory device 102 can include TSVs 122 electrically coupling the master device 104 and the slave devices 106. The master device 104 can communicate with the controller 103 for implementing the commands/operations.
The master device 104 and/or the slave devices 106 can each include core test logic 132 configured to facilitate the testing of the die. Additionally, the master device 104 and/or the slave devices 106 can each include operational core 134 configured to carry out the operations, such as the memory operations.
FIG. 2 illustrates a block diagram of a memory device 200 (e.g., the memory device 102 or a portion thereof). The memory device 200 can include a strobe circuit 202, a latch circuit 204, etc. The strobe circuit 202 can be configured to receive/process a data strobe set 210, such as for a set of clock signals. The latch circuit 204 (e.g., a serial-to-parallel first-in first-out (FIFO) device/buffer) can convert a format/sequence of the received data signal.
For example, for write cycles, the intended write data (data input set) can be communicated in bursts/groups (e.g., groups of four data bits, and in some cases, two additional bits for cyclic redundancy check (CRC) information). The strobe circuit 202 can internally generate/communicate the data strobe set 210 that act as clock signals for latching/converting the received/data signal at the latch circuit 204.
The strobe circuit 202, the latch circuit 204, etc. can include components dedicated/configured to single data segment (e.g., bit) within the data strobe set 210. For example, the data strobe set 210 can include a first strobe signal 211 (DQS2), a second strobe signal 212 (DQS3), a third strobe signal 213 (DQS6), a fourth strobe signal 214 (DQS7), a fifth strobe signal 215 (DQS8), a sixth strobe signal 216 (DQS9), etc. Accordingly, the strobe circuit 202 can include a first timing circuit 221 corresponding to the first strobe signal 211, a second timing circuit 222 corresponding to the second strobe signal 212, a third timing circuit 223 corresponding to the third strobe signal 213, a fourth timing circuit 224 corresponding to the fourth strobe signal 214, a fifth timing circuit 225 corresponding to the fifth strobe signal 215, a sixth timing circuit 226 corresponding to the sixth strobe signal 216, etc.
The latch circuit 204 can include a first latch 241, a second latch 242, a third latch 243, a fourth latch 244, a fifth latch 245, a sixth latch 246, etc. each configured to latch a component/portion of a data input set 250 (e.g., intended write data or write payload). For example, the first latch 241, the second latch 242, the third latch 243, the fourth latch 244, the fifth latch 245, the sixth latch 246, etc. can latch a first data 251, a second data 252, a third data 253, a fourth data 254, a fifth data 255, a sixth data 256, etc. respectively. Each of the latches can receive the corresponding strobe signal (e.g., the first strobe signal 211, the second strobe signal 212, the third strobe signal 213, the fourth strobe signal 214, the fifth strobe signal 215, the sixth strobe signal 216, etc. respectively) and use it to latch the data signals.
For some DRAM devices, burst operations and page-gapless operations can be implemented for various operations, such as during write cycles. Accordingly, the devices can communicate multiple bits in groups/bursts for the operations. The information (e.g., bits) communicated during the bursts (e.g., eight data bits or strings of data bits) can be continuously processed, such as based on a serial-to-parallel conversion. Each of the communicated bit can correspond to relative timings (e.g., data strobe clocks or DQS) that require certain characteristics (e.g., setup time and hold time). At high frequencies, the windows for these critical times become narrower. Further, when the device is a stacked master/slave device that includes multiple stacked dies, signals for all of the slave devices flow through the master device. The signals can have various timing/waveform discrepancies, such as due to power bus noise, signal couplings, data propagation, process/temperature/voltage variations, etc. in circuits.
The variations in timing/waveform shapes, etc. can further reduce the effectiveness of the critical times as they are processed through the master device with stacks of slave devices' parasitic resistance and capacitance loadings. For example, the strobe signals (e.g., DQS 2/3/6/7/8/9/etc.) and the data (e.g., DQ 1/2/3/4/5/6/etc.) can be sent from the master device to the slave devices. If the DRAM device is 2H/4H/8H/16H, the increased number of devices within a stack will increase the overall resistance and capacitive loading that will introduce variations. The master device and each of the slave devices have their own variations resulting from process/voltage/temperature (PVT), where the variations further reduce the setup time and the hold time. Moreover, variations can occur between each of the strobe signals, such as between DQS2 and DQS3.